The present invention relates to the fabrication of vertical bipolar junction transistors, and more particularly to fabricating vertical bipolar junction transistors in a single crystal silicon wafer bonded to an insulating substrate such as sapphire.
Bipolar junction transistors (BJT's) and diodes have been fabricated in silicon-on-sapphire (SOS) films with varying degrees of success. Most research has been concentrated in the area of lateral BJT's, epitaxial silicon grown BJT's, and heteroepitaxy BJT's. Lateral bipolar devices fabricated in SOS have low cutoff frequencies and are not suitable for driving large amounts of current. Also, due to the low carrier lifetime material, lateral devices historically have had low current gain. Vertical BJT's fabricated in SOS have traditionally suffered from low current and low recombination lifetimes due to the poor quality of crystal structure of the silicon.
U.S. Pat. No. 3,974,560 describes a process for manufacturing planar bipolar transistors which includes ion implanting a collector contact well in a layer of single crystal silicon epitaxially grown on an insulating substrate such as sapphire. Then the silicon layer is annealed for about 15 minutes at a temperature in the range of about 900 .degree. C. to 1100 .degree. C.
It is well known that epitaxially grown silicon is different from "bulk" silicon. First, silicon deposited epitaxially on sapphire does not exhibit the crystal perfection of a bulk, single-crystal silicon wafer. Further, the region of epitaxially grown silicon nearest the sapphire substrate is not a good semiconductor.
Another difference which distinguishes SOS from bulk single crystal silicon is the relatively higher density of crystal lattice defects found in silicon epitaxially grown on sapphire, manifesting in very low minority carrier lifetimes. Lifetimes in the range of about 0.1-10 nanoseconds are typical for such SOS layers, whereas in bulk silicon, minimum carrier lifetimes are about 10 nanoseconds and carrier lifetimes in general typically range from about 100 nanoseconds to 1 microsecond.
Still another difference between the silicon in a conventional SOS structure and bulk silicon is the uncontrolled nature of the impurity diffusion constant in the SOS structure. Activation energies required to move an atom out of position in the crystal lattice of an SOS structure are generally lower and not as uniform and controlled as they are in bulk silicon. Hence, fast, localized diffusion occurs much more easily in SOS, tending to short out the junction of bipolar device made in SOS. This is especially true for SOS bipolar transistors because the emitter-collector separation distance must be very small and because the carrier lifetime is so short.
Thus, it may be appreciated that the electrical performance of a bipolar transistor fabricated in accordance with the methods of the '560 patent is limited by the characteristic of epitaxially grown silicon.
Silicon and sapphire have vastly different coefficients of thermal expansion. For example, the coefficient of thermal expansion of silicon is 3.6.times.10.sup.-6 /.degree.C., and that of sapphire is 5.0.times.10.sup.-6 /.degree.C. Because of this difference, SOS structures subjected to large temperature differentials tend to exhibit thermally induced cracks in the vicinity of the silicon and sapphire interface. Such cracks prevent the manufacture of operable devices. Because the SOS structure described in the '560 patent is subject to a relatively high temperature anneal (900-1100.degree. C.), it is particularly vulnerable to thermal cracking.
Thus, it may be appreciated that there is a need for a method for manufacturing bipolar transistors using single crystal, bulk silicon and which does not require high temperature processing. Such a method would produce bipolar transistors having superior performance over bipolar transistors manufactured using conventional methods.